1. Field of the Invention
The present invention relates to an access processing system in an information processor and more particularly, to an access processing system that can mitigate competition between data buses in the course of accessing a memory device.
2. Description of the Related Art
In recent years, with the increased popularity of information processing equipment such as computers, there has been a demand for a reduction in cost and increased operating speeds.
In general, such information processors are constituted such that a central processing unit (abbreviated CPU) and its peripheral equipment such as a memory device, an input/output device or the like are connected mutually by a bus. When a CPU provides an access to the peripheral, the transfer of data is realized by delivering/receiving an address, data or a command (access mode) via a bus. Therefore, a more effective utilization of the buses is desired to improve system performance.
In the prior art, when an explicit write access is carried out with regard to a storage key device, since an address must be held until a write operation of write data to a predetermined address of the storage key device has been completed, it is disadvantageous that a monitoring of the address cannot be carried out in the meantime and the delivery of the new address must be inhibited. Further, when a prior read access is created and the delivery of write data is suspended, an access of another CPU must be inhibited, and even if there is no suspension of the delivery of write data, since an access operation is inhibited for a specified time and it is necessary to have a CPU that requires access to a system storage device, the system's performance deteriorates.